(a) Field of the Invention
The present invention relates to a method of forming damascene pattern in a semiconductor device, and particularly to a method of forming damascene pattern, which is able to minimize the change of critical dimension of a damascene mask according to the via/contact density.
(b) Description of Related Art
Recently, copper (Cu) wiring process is suggested to improve characteristics of a semiconductor device such as operation speed, resistance, parasitic capacitance between metal layers, while semiconductor devices become integrated and the fabrication technique is advanced. For insulating films, material having low-k (dielectric constant) is highlighted instead of the conventional oxide films for the wiring process of the next generation device.
However, the wring process using copper and material having low-k has a disadvantage that etching characteristic of copper is very poor. In this regard, a method of forming damascene pattern in which via holes and trenches are formed by via etching and trench etching and filled with copper as disclosed in U.S. Pat. No. 5,635,423 is known as proper for copper wiring.
However, the conventional method of forming damascene pattern has problems listed below.
One of the methods of forming damascene pattern is shown in FIGS. 1 and 2. To form a damascene pattern, as shown in FIGS. 1 and 2, a bottom wiring 10 is formed on a semiconductor substrate (not shown), a thick oxide layer 20 is deposited thereon, via holes 25 are formed in the oxide layer 20 using via etching, a bottom anti-reflection layer 30 is deposited on the surfaces of the oxide layer 20 and the via holes 25, and trenches (not shown) are formed using a mask pattern 40 for trench etching.
According to the above method of forming damascene pattern, the bottom anti-reflection layer 30 in the area A1 placed on the left side of FIG. 1, i.e. the area with low via hole density is deposited to become thicker than that in the other area A2 placed on the right side of FIG. 1, i.e. the area with high via hole density.
That is, the thickness T of the bottom anti-reflection layer 30 deposited on the area A1 with low via hole density exceeds the thickness T′ on the area A2 with high via hole density.
In case that the thickness T and T′ of the bottom anti-reflection layer 30 are different (T≠T′), width of a mask pattern 40 for trench etching in the area A1 with low via hole density becomes very different from that in the area A2 with high via hole density (W<<W′) when the mask pattern 40 for trench etching is formed.
Therefore, the critical dimension CD of the damascene pattern 50 in the area A1 with low via hole density becomes very different from that in the area A2 with high via hole density (CD<<CD′) due to the difference of the width of the mask pattern 40 for trench etching depending on via hole density as described above. In result, reliability of the device becomes low due to the low CD uniformity.